Digital Twin of a Dynamic Power Semiconductor Tester
2024-2025 tavasz
Hardver (és szoftver firmware)
Téma leírása
This master thesis focuses on the creation of a digital twin for a dynamic power semiconductor tester specifically designed for Silicon Carbide (SiC) MOSFETs with fast slopes. These devices help to improve the efficiency of converters and power supplies.
This thesis aims to develop a comprehensive digital twin model of the power semiconductor tester which focuses on the hardware setup. High frequency components of the slopes require modelling of parasitic elements. Therefore, the main parasitic elements of the tester should be estimated in the first step. A suitable Spice model should be developed afterwards. The model should be validated by real testing data.
Külső partner: Infineon Technologies AG
Maximális létszám:
1 fő